1. Field of the Invention
The present invention relates to semiconductor devices, and also relates to a semiconductor device which is arranged to flow a current from a first diffusion region toward a second diffusion region, which are formed on the top surface side of a semiconductor substrate, and further flow such current to an electrode formed at a back surface of the semiconductor substrate.
2. Description of the Related Art
The structure of a lateral type n-channel MISFET which is as one example of semiconductor devices of the type stated above is known from JP-A-2003-31805 (Paragraphs [0009] to [0014] and FIG. 25, etc.) for example. This structure will be explained while referring to FIG. 7 and FIG. 8. FIG. 7 is a diagram showing a plan view of the lateral type n-channel MISFET, and FIG. 8 is a cross-sectional view as taken along line A–A′ of FIG. 7. In this MISFET, an epitaxial layer 40 of p− type is formed on or above a semiconductor substrate 30 of p+ type made of silicon, by way of example. The layer 40 is higher in electrical resistance than the semiconductor substrate 30 and is different in gradient of impurity concentration from the semiconductor substrate. On this epitaxial layer 40, a drain diffusion layer 50 of n type is formed. The drain diffusion layer 50 is designed to have a lightly doped drain (LDD) structure having high resistance drain layers 50A (high resistance layers) which are placed at the both ends and are low in impurity concentration and a low resistance drain layer 50B (low resistance layer) which resides at a central portion and is high in impurity concentration. The low resistance drain layer 50B is arranged to have high impurity concentration for purposes of reduction of contact resistance between it and a drain electrode 55; on the other hand, the high resistance drain layer 50A is low in impurity concentration in order to prevent reduction of withstand or “breakdown” voltage.
Base diffusion layers 70 of p type are formed at the both edge portions of this drain diffusion layer 50. A gate electrode 75 is formed through a dielectric film 76 at a position neighboring upon the high resistance drain layer 50A that overlies this base diffusion layer 70. At the base diffusion layer 70 immediately underlying this gate electrode 75, a channel section 71 is formed by control of a gate voltage. As shown in FIG. 7, the gate electrode 75 is arranged to extend at right angles toward the direction of each circuit element from a gate electrode wiring line 75T. The gate electrode wiring line 75T is applied a gate voltage from a wiring line 75W and a contact portion 75C.
A source diffusion layer 80 of n type is formed above the base diffusion layer 70 in such a manner that this layer is symmetrical with the drain diffusion layer 50, with the gate electrode 75 being interposed therebetween. This source diffusion layer 80 is electrically connected to a short-circuit electrode 85 (a source electrode), together with the base diffusion layer 70. The drain electrode 55, gate electrode 75 and short-circuit electrode 85 are electrically insulated or isolated from one another by a dielectric film 86. The short-circuit electrode 85 is electrically coupled to a contact layer 90 of heavily doped p (p+) type, which is formed to penetrate the epitaxial layer 40 to reach the semiconductor substrate 30, whereby it is short-circuited to the gate electrode 75 and a source electrode 100 that is formed on the back surface of the semiconductor substrate 30. The drain diffusion layer 50, base diffusion layer 70, source diffusion layer 80 and contact layer 90 are fabricated by a photolithography process including the steps of selectively implanting an impurity onto the epitaxial layer 40 and then diffusing the impurity by thermal processing.
In this arrangement, when giving the gate electrode 75 a gate voltage greater than or equal to the threshold voltage, a channel is formed in the channel section 71, causing electrons for use as carriers to flow from the drain electrode 55 toward the short-circuit electrode 85 through the drain diffusion layer 50 and channel section 71 plus source diffusion layer 80. Thus, a current with positive holes (holes) being as carriers flows from the short-circuit electrode 85 to the source electrode 100.
In this lateral type MISFET shown in FIGS. 7 and 8, the high resistance drain layer 50A is arranged so that its lateral width X is set at an appropriate value by taking into consideration any possible drop-down of the withstand voltage and rise-up of turn-on (ON) resistance. More specifically, in order to lower the ON resistance of MISFET, it is desirable that the width X be as short as possible. However, when the width X becomes shorter, the withstand voltage dropdown becomes problematic. Due to this, in the lateral type MISFET shown in FIGS. 7–8, design is done to minimize the width X within a certain range in which the withstand voltage required is obtainable.
In the lateral type MISFET with the width X shortened in this way and with the epitaxial layer 40 being made greater in thickness Y in comparison with this X value, when applying a reverse bias voltage (setting the drain electrode 55 at a positive voltage and letting the gate electrode 75 and source electrode 100 be grounded), the resultant electric field tends to most concentrate on terminate end portions of the gate electrode 75 that is in contact with the drain diffusion layer 50. As a result, “hot” carriers are injected into the gate electrode 75 beyond the dielectric film 76's potential barrier. This would result in occurrence of fluctuation of the threshold voltage of such gate. Additionally, upon injection of the hot carriers, the high resistance drain layer 50A decreases in carrier density or concentration, whereby there is a problem that the ON resistance increases.